By: Howard Goldstein - HomePage Hey another thing you may wish to consider mentioning are the bugs in the NMOS version of the CPU. One of them is with regard to the buggy IFF2->parity flag performance in the LD A,I and LD A,R instructions. An error can occur when an INTACK runs near these instructions: the parity flag will be showing 0 when it should have been 1. A Zilog app note is around somewhere talking about this. It's a rather nasty bug for embedded apps... There are I think a few others.
Z80 Undocumented Instructions..
By: Jacco J.T. Bot At your request for documentation on the extra z80 instructions I've dug into my subdirectories and out came a file which is listed below. I hope it helps understanding the Z80, most instructions are a direct result of the way it is microcoded. That is also visible in an instruction like LD A,HL. There is the 3-byte fast function and the #ED prefix one, which is considerably slower but implemen- ted anyway when the Great ChipMaker decided to expand the in- structionset with LD A,BC; LD A,DE; The way these instructions are decoded implements automatically the LD A,HL instruction for the second time. Why Zilog is silent about the next bunch of instructions is a mystery to me. But they also make the Z800, the Z8000, the Z180, the Z280 and the Z380 which must al be compatible on instruction level so maybe the extra z80 instructions aren't implemented in one of these. Who cares anyway, lets get to the :) Undocumented Z80 instructions ---------------------------------------------- If an opcode works with the registers HL, H or L then if that opcode is preceded by #DD (or #FD) it works on IX, IXH or IXL (or IY, IYH, IYL), with some exceptions. The exeptions are instructions like LD H,IXH and LD L,IYH because it isn't clear from the opcode on which register the prefix (#FD or #DD) should operate, so from the opcodes point of view we can read LD H,IXH but also LD IXH, H and obviously LD IXH,IXH doesn't do us any good, does it? Instructions like LD IXH,IXL should work but I didn't test them yet, my debugger went bananas and is now retired to the afterlife for computerprograms... I also have doubts about the usefullness and correctness of the OUT (C),F instruction. The IN (C), F instructions is only usefull if you test bits which have the same number as a flag in the F-register because some older Z80 lock up otherwise. An instruction which uses the #ED and the #DD (or #FD) prefix is also invalid, so IN IXH,(C) which should translate to DD ED .. is NOT valid. Anyway, here's a list of valid, but undocumented by Zilog, instructions... These instructions are tested on: Z80A, Z80B and Z80H. OPCODE INSTRUCTION OPCODE INSTRUCTION ----------- ----------------- ------------ ------------ #DD #24 INC IXH #FD #24 INC IYH #DD #25 DEC IXH #FD #25 DEC IYH #DD #26 nn LD IXH,nn #FD #26 nn LD IYH,nn #DD #2C INC IXL #FD #2C INC IYL #DD #2D DEC IXL #FD #2D DEC IYL #DD #2E nn LD IXL,nn #FD #2E nn LD IYL,nn #DD #44 LD B,IXH #FD #44 LD B,IYH #DD #45 LD B,IXL #FD #45 LD B,IYL #DD #4C LD C,IXH #FD #4C LD C,IYH #DD #4D LD C,IXL #FD #4D LD C,IYL #DD #54 LD D,IXH #FD #54 LD D,IYH #DD #55 LD D,IXL #FD #55 LD D,IYL #DD #5C LD E,IXH #FD #5C LD E,IYH #DD #5D LD E,IXL #FD #5D LD E,IYL #DD #60 LD IXH,B #FD #60 LD IYH,B #DD #61 LD IXH,C #FD #61 LD IYH,C #DD #62 LD IXH,D #FD #62 LD IYH,D #DD #63 LD IXH,E #FD #63 LD IYH,E #DD #64 LD IXH,IXH #FD #64 LD IYH,IYH #DD #65 LD IXH,IXL #FD #65 LD IYH,IYL #DD #67 LD IXH,A #FD #67 LD IYH,A #DD #68 LD IXL,B #FD #68 LD IYL,B #DD #69 LD IXL,C #FD #69 LD IYL,C #DD #6A LD IXL,D #FD #6A LD IYL,D #DD #6B LD IXL,E #FD #6B LD IYL,E #DD #6C LD IXL,IXH #FD #6C LD IYL,IYH #DD #6D LD IXL,IXL #FD #6D LD IYL,IYL #DD #6F LD IXL,A #FD #6F LD IYL,A #DD #7C LD A,IXH #FD #7C LD A,IYH #DD #7D LD A,IXL #FD #7D LD A,IYL #DD #84 ADD A,IXH #FD #84 ADD A,IYH #DD #85 ADD A,IXL #FD #85 ADD A,IYL #DD #8C ADC A,IXH #FD #8C ADC A,IYH #DD #8D ADC A,IXL #FD #8D ADC A,IYL #DD #94 SUB IXH #FD #94 SUB IYH #DD #95 SUB IXL #FD #95 SUB IYL #DD #9C SBC A,IXH #FD #9C SBC A,IYH #DD #9D SBC A,IXL #FD #9D SBC A,IYL #DD #A4 AND IXH #FD #A4 AND IYH #DD #A5 AND IXL #FD #A5 AND IYL #DD #AC XOR IXH #FD #AC XOR IYH #DD #AD XOR IXL #FD #AD XOR IYL #DD #B4 OR IXH #FD #B4 OR IYH #DD #B5 OR IXL #FD #B5 OR IYL #DD #BC CP IXH #FD #BC CP IYH #DD #BD CP IXL #FD #BD CP IYL #DD #CB nn #00 RLC (IX+nn) & LD B,(IX+nn) 1) #DD #CB nn #01 RLC (IX+nn) & LD C,(IX+nn) #DD #CB nn #02 RLC (IX+nn) & LD D,(IX+nn) #DD #CB nn #03 RLC (IX+nn) & LD E,(IX+nn) #DD #CB nn #04 RLC (IX+nn) & LD H,(IX+nn) #DD #CB nn #05 RLC (IX+nn) & LD L,(IX+nn) #DD #CB nn #06 RLC (IX+nn) & LD F,(IX+nn) #DD #CB nn #07 RLC (IX+nn) & LD A,(IX+nn) #DD #CB nn #08 RRC (IX+nn) & LD B,(IX+nn) etc. #DD #CB nn #10 RL (IX+nn) & LD B,(IX+nn) etc. #DD #CB nn #18 RR (IX+nn) & LD B,(IX+nn) etc. #DD #CB nn #20 SLA (IX+nn) & LD B,(IX+nn) etc. #DD #CB nn #28 SRA (IX+nn) & LD B,(IX+nn) etc. #DD #CB nn #30 SLL (IX+nn) & LD B,(IX+nn) etc. #DD #CB nn #38 SRL (IX+nn) & LD B,(IX+nn) etc. #DD #CB nn #80 RES 0,(IX+nn) & LD B,(IX+nn) etc. #DD #CB nn #88 RES 1,(IX+nn) & LD B,(IX+nn) etc. #DD #CB nn #90 RES 2,(IX+nn) & LD B,(IX+nn) etc. #DD #CB nn #98 RES 3,(IX+nn) & LD B,(IX+nn) etc. #DD #CB nn #A0 RES 4,(IX+nn) & LD B,(IX+nn) etc. #DD #CB nn #A8 RES 5,(IX+nn) & LD B,(IX+nn) etc. #DD #CB nn #B0 RES 6,(IX+nn) & LD B,(IX+nn) etc. #DD #CB nn #B8 RES 7,(IX+nn) & LD B,(IX+nn) etc. #DD #CB nn #C0 SET 0,(IX+nn) & LD B,(IX+nn) etc. #DD #CB nn #C8 SET 1,(IX+nn) & LD B,(IX+nn) etc. #DD #CB nn #D0 SET 2,(IX+nn) & LD B,(IX+nn) etc. #DD #CB nn #D8 SET 3,(IX+nn) & LD B,(IX+nn) etc. #DD #CB nn #E0 SET 4,(IX+nn) & LD B,(IX+nn) etc. #DD #CB nn #E8 SET 5,(IX+nn) & LD B,(IX+nn) etc. #DD #CB nn #F0 SET 6,(IX+nn) & LD B,(IX+nn) etc. #DD #CB nn #F8 SET 7,(IX+nn) & LD B,(IX+nn) etc. #CB #30 SLL B 2) #CB #31 SLL C #CB #32 SLL D #CB #33 SLL E #CB #34 SLL H #CB #35 SLL L #CB #36 SLL (HL) #CB #37 SLL A #ED #70 IN F,(C) #ED #71 OUT F,(C) (?) All the above instructions also work with IY, IYH and IYL, just replace #DD for #FD. NOTES: 1) These instructions are strange because in fact they are two instructions in one. Lets examine the folowing line #DD #CB nn #00 RLC (IX+nn) & LD B,(IX+nn) The value at address (IX+nn) is left rotated through the carry AND is loaded in the B register. I bet that some sophisticated programmers may make excellent use of these commands but I reccomend against using them because its task it not obvious from the opcode, and my assembler doesn't (YET) support them, I've got to find a nice short symbol for them, maybe something like RLC(IX+nn)->B. 2) These instructions are equivalent to the SLA command. That is perfectly logical: An arithmethic rightshift (SRA) has to preserve the 7-th (sign)bit, A logical rightshift (SRL) doesn't. The arithmetic leftshift doesn't preserve anything, in two's complement the 6-th bit becomes the sign. A logical leftshift hasn't got anything to do with signbits so it also doesn't preserve any bits. The difference is the way we look at the resulting number, a 8-bit byte or a 7-bit integer with 1 sign-bit. Original list by Richard Spijkers, 1992 ricosoftware. Translated and Updated by Jacco Bot, 1996 JBSoft By the way, The W95 assembler for the z80 is available at: www.msx.org/~sandervn/msx.html You just click the JBSOFT at the bottom of the page and then Other JBSOFT products at the next page, then you will see a nice screenshot and be able to download the program. GreetinX, Jacco